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IDT5992A PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCKTM
* 4 pairs of programmable skew outputs * Low skew: 200ps same pair, 250ps all outputs * Selectable positive or negative edge synchronization: Excellent for DSP applications * Synchronous output enable * Output frequency: 3.75MHz to 100MHz * 2x, 4x, 1/2, and 1/4 outputs * 5V with CMOS outputs * 3 skew grades: IDT5992A-2: tSKEW0<250ps IDT5992A-5: tSKEW0<500ps IDT5992A-7: tSKEW0<750ps * 3-level inputs for skew and PLL range control * PLL bypass for DC testing * External feedback, internal loop filter * 46mA IOL high drive outputs * Low Jitter: <200ps peak-to-peak * Outputs drive 50 terminated lines * Pin-compatible with Cypress CY7B992 * Available in PLCC Package
IDT5992A
FEATURES:
The IDT5992A is a high fanout PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5992A has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels. The IDT5992A maintains Cypress CY7B992 compatibility while providing two additional features: Synchronous Output Enable (GND/sOE), and Positive/Negative Edge Synchronization (VDDQ/PE). When the GND/ sOE pin is held low, all the outputs are synchronously enabled (CY7B992 compatibility). However, if GND/sOE is held high, all the outputs except 3Q0 and 3Q1 are synchronously disabled. Furthermore, when the VDDQ/PE is held high, all the outputs are synchronized with the positive edge of the REF clock input (CY7B992 compatibility). When VDDQ/PE is held low, all the outputs are synchronized with the negative edge of REF.
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
G N D /sO E
S ke w S e le ct 3 3 1 F 1 :0 V D D Q /P E S ke w S e le ct REF PLL FB 3 FS S ke w S e le ct 3 3 3 F 1 :0 3 3 2 F 1 :0
1Q0 1Q1
2Q0 2Q1
3Q0 3Q1
S ke w S e le ct 3 3 4 F 1 :0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
4Q0 4Q1
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c 2001 Integrated Device Technology, Inc.
AUGUST 2001
DSC 5391/1
IDT5992A PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
GND TEST VDDQ REF 3F0 2F1 FS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VI Description Supply Voltage to Ground DC Input Voltage Maximum Power Dissipation (TA = 85C) TSTG Storage Temperature Max -0.5 to +7 -0.5 to +7 0.8 -65 to +150 Unit V V W C
4 3F1 4F0 4F1 VDDQ/PE VDDN 4Q1 4Q0 GND GND 5 6 7 8 9 10 11 12 13 14
3
2
1
32
31
30 29 28 27 26 25 24 23 22 21 2F0 GND/sOE 1F1 1F0 VDDN 1Q0 1Q1 GND GND
NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
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CAPACITANCE(TA = +25C, f = 1MHz, VIN = 0V)
Parameter CIN Description Input Capacitance Typ. 5 Max. 7 Unit pF
VDDN
VDDN
3Q0
3Q1
FB
2Q1
2Q0
PLCC TOP VIEW
NOTE: 1. Capacitance applies to all inputs except TEST, FS, and nF1:0.
PIN DESCRIPTION
Pin Name REF FB TEST (1) GND/ sOE (1) Type IN IN IN IN Description Reference Clock Input Feedback Input When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control Summary Table) remain in effect. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and GND/sOE is HIGH, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set GND/sOE LOW for normal operation. VDDQ/PE nF[1:0] FS nQ[1:0] VDDN VDDQ GND IN IN IN OUT PWR PWR PWR Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock. 3-level inputs for selecting 1 of 9 skew taps or frequency functions Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.) Four banks of two outputs with programmable skew Power supply for output buffers Power supply for phase locked loop and other internal circuitry Ground
NOTE: 1.When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL.
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit tU which is of the order of a nanosecond (see PLL Programmable Skew Range and Resolution Table). There are nine skew configurations available for each output pair. These configurations are chosen by the nF1:0 control pins. In order 2 to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for but not restricted to hard-wiring. Undriven 3-level inputs default to the MID level. Where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. The Control Summary Table shows how to select specific skew taps by using the nF1:0 control pins.
IDT5992A PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
EXTERNAL FEEDBACK
By providing external feedback, the IDT5992A gives users flexibility with regard to skew adjustment. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
FS = LOW Timing Unit Calculation (tU) VCO Frequency Range (FNOM)(1,2) Skew Adjustment Range(3) Max Adjustment: 9.09ns 49 14% Example 1, FNOM = 15MHz Example 2, FNOM = 25MHz Example 3, FNOM = 30MHz Example 4, FNOM = 40MHz Example 5, FNOM = 50MHz Example 6, FNOM = 80MHz tU = 1.52ns tU = 0.91ns tU = 0.76ns -- -- -- 9.23ns 83 23% -- tU = 1.54ns tU = 1.28ns tU = 0.96ns tU = 0.77ns -- 9.38ns 135 37% -- -- -- tU = 1.56ns tU = 1.25ns tU = 0.78ns ns Phase Degrees % of Cycle Time 1/(44 x FNOM) 15 to 35MHz FS = MID 1/(26 x FNOM) 25 to 60MHz FS = HIGH 1/(16 x FNOM) 40 to 100MHz Comments
NOTES: 1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on input frequency range allows the PLL to operate in its `sweet spot' where jitter is lowest. 2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided output as the FB input. 3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed -4tU in addition to whatever skew value is programmed for those outputs. `Max adjustment' range applies to output pairs 3 and 4 where 6tU skew adjustment is possible and at the lowest FNOM value.
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0 LL(1) LM LH ML MM MH HL HM HH Skew (Pair #1, #2) -4tU -3tU -2tU -1tU Zero Skew 1tU 2tU 3tU 4tU Skew (Pair #3) Divide by 2 -6tU -4tU -2tU Zero Skew 2tU 4tU 6tU Divide by 4 Skew (Pair #4) Divide by 2 -6tU -4tU -2tU Zero Skew 2tU 4tU 6tU Inverted(2)
NOTES: 1. LL disables outputs if TEST = MID and GND/sOE = HIGH. 2. When pair #4 is set to HH (inverted), GND/sOE disables pair #4 HIGH when VDDQ/PE = HIGH, GND/sOE disables pair #4 LOW when VDDQ/PE = LOW.
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IDT5992A PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RECOMMENDED OPERATING RANGE
IDT5992A-5, -7 (Industrial) Symbol VDD TA Description Power Supply Voltage Ambient Operating Temperature Min. 4.5 -40 Max. 5.5 +85 IDT5992A-2 (Commercial) Min. 4.75 0 Max. 5.25 +70 Unit V C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol VIH VIL VIHH VIMM VILL IIN Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Voltage(1) Input MID Voltage
(1)
Conditions Guaranteed Logic HIGH (REF, FB Inputs Only) Guaranteed Logic LOW (REF, FB Inputs Only) 3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only VIN = VDD or GND VDD = Max. VIN = VDD HIGH Level MID Level LOW Level
Min. VDD-1.35 -- VDD-1 VDD/2-0.5 -- -- -- -- -- -- -- -- VDD-0.75 -- --
Max. -- 1.35 -- VDD/2+0.5 1 5 200 50 200 100 100 -- -- 0.45 N/A
Unit V V V V V A
Input LOW Voltage(1) Input Leakage Current (REF, FB Inputs Only)
I3 IPU IPD VOH VOL IOS
3-Level Input DC Current (TEST, FS, nF1:0) Input Pull-Up Current (VDDQ/PE) Input Pull-Down Current (GND/sOE) Output HIGH Voltage Output LOW Voltage Output Short Circuit
(2)
VIN = VDD/2 VIN = GND VDD = Max., VIN = GND VDD = Max., VIN = VDD VDD = Min., IOH = -16mA VDD = Min., IOH = -40mA VDD = Max., VO = GND VDD = Min., IOL = 46mA
A A A V V mA
NOTES: 1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. 2. This output is not to be shorted.
POWER SUPPLY CHARACTERISTICS
Symbol IDDQ IDD IDDD ITOT Parameter Quiescent Power Supply Current Power Supply Current per Input HIGH Dynamic Power Supply Current per Output Total Power Supply Current Test Conditions(1) VDD = Max., TEST = MID, REF = LOW, GND/sOE = LOW, All outputs unloaded VDD = Max., VIN = 3.4V VDD = Max., CL = 0pF VDD = 5V, FREF = 20MHz, CL = 240pF(1) VDD = 5V, FREF = 33MHz, CL = 240pF(1) VDD = 5V, FREF = 66MHz, CL =
NOTE: 1. For eight outputs, each loaded with 30pF.
Typ.(2) 10 0.4 100 43 63 117
Max. 40 1.5 160 -- -- --
Unit mA mA A/MHz mA
240pF(1)
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IDT5992A PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
INPUT TIMING REQUIREMENTS
Symbol tR, tF tPWC DH REF Description (1) Maximum input rise and fall times, 0.8V to 2V Input clock pulse, HIGH or LOW Input duty cycle Reference Clock Input Min. -- 3 10 3.75 Max. 10 -- 90 100 Unit ns/V ns % MHz
NOTE: 1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT5992A-2 Symbol FNOM tRPWH tRPWL tU tSKEWPR tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tDEV tPD tODCV tPWH tPWL tORISE tOFALL tLOCK tJR Parameter VCO Frequency Range REF Pulse Width HIGH(1) REF Pulse Width LOW
(1)
IDT5992A-5 Max. -- -- 0.2 0.25 0.5 1.2 0.5 0.9 0.75 0.25 0.5 3 3 2.5 2.5 0.5 25 200 Min. 3 3 -- -- -- -- -- -- -- Typ. -- -- 0.1 0.25 0.6 0.6 0.5 0.6 -- 0 0 -- -- 2 2 -- -- -- Max. -- -- 0.25 0.5 0.7 1.5 0.7 1.7 1.25 0.5 1.2 4 4 3.5 3.5 0.5 25 200 Min. 3 3 -- -- -- -- -- -- --
IDT5992A-7 Typ. -- -- 0.1 0.3 0.6 0.5 0.7 1.2 -- 0 0 -- -- 3 3 -- -- -- Max. -- -- 0.25 0.75 1 1.5 1.2 1.7 1.65 0.7 1.5 5.5 5.5 5 5 0.5 25 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ps
Min. 3 3 -- -- -- --
(1,6)
Typ. -- -- 0.05 0.1 0.25 0.5 0.25 0.5 -- 0 0 -- -- 2 2 -- -- --
See PLL Programmable Skew Range and Resolution Table
Programmable Skew Time Unit Zero Output Matched-Pair Skew (xQ0, xQ1)(1,2,3) Zero Output Skew (All Outputs) Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)(1,3) Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided) Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)(1,6) Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)(1,2) Device-to-Device Skew(1,2,7) REF Input to FB Propagation Delay
(1,9) (1,4,5)
See Control Summary Table
-- -- --
Output Duty Cycle Variation from 50%(1) Output HIGH Time Deviation from 50% Output Rise Time Output Fall Time PLL Lock Time(8) Cycle-to-Cycle Output Jitter(1) RMS Peak-to-Peak
(1) (1,10)
-0.25 -0.5
-- -- 0.5 0.5 -- -- --
-0.5 -1.2
-- -- 0.5 0.5 -- -- --
-0.7 -1.5
-- -- 0.5 0.5 -- -- --
Output LOW Time Deviation from 50%(1,11)
(1)
NOTES: 1. All timing and jitter tolerances apply for FNOM > 25MHz. 2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load. 3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. 4. tSKEW0 is the skew between outputs when they are selected for 0tU. 5. For IDT5992A-2 tSKEW0 is measured with CL = 0pF; for CL = 30pF, tSKEW0 = 0.45ns Max. 6. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divideby-4 mode). 7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDD ambient temperature, air flow, etc.) 8. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 9. tPD is measured with REF input rise and fall times (from 0.2VDD to 0.8VDD ) of 1.5ns. 10. Measured at 0.8VDD. 11. Measured at 0.2VDD.
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IDT5992A PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC TEST LOADS AND WAVEFORMS
VDD
100 Output
100
CL
CL = 50pF (CL = 30pF for -2 and -5 devices)
Test Load
tORISE
0.8VDD
tOFALL
tPWH tPWL
0.2VDD
CMOS Output Waveform
1.5ns
1.5ns
VDD 80% Vth = 0.5VDD 20% 0V
CMOS Input Test Waveform
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IDT5992A PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC TIMING DIAGRAM
tREF tRPWH
REF
tRPWL
tPD
FB
tODCV
tODCV
tJR
Q
tSKEWPR tSKEW0, 1
OTH ER Q
tSKEWPR tSKEW0, 1
tSKEW2
INVER TED Q
tSKEW2
tSKEW3, 4 tSKEW3, 4
REF D IVIDED BY 2
tSKEW3, 4
tSKEW1, 3, 4
tSKEW2, 4
REF D IVIDED BY 4
NOTES: VDDQ/PE: The AC Timing Diagram applies to VDDQ/PE=VDD. For VDDQ/PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align. Skew: tSKEWPR: tSKEW0: tDEV: tODCV: The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 50pF (30pF for -2 and -5) and terminated with 50 to VDD/2. The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. The skew between outputs when they are selected for 0tU. The output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow, etc.) The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tPWH is measured at 0.8VDD. tPWL is measured at 0.2VDD. tORISE and tOFALL are measured between 0.2VDD and 0.8VDD. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
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IDT5992A PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Process
Blank I J
Commercial (0C to +70C) Industrial (-40C to +85C) Rectangular Plastic Leaded Chip Carrier
5992A-2 5992A-5 5992A-7
Programmable Skew PLL Clock Driver TurboClock
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